A Unified Framework for Equivalence Verification of Datapath Oriented Applications

In this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to a gate-level implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of the gate-level implementation. Our HED can support modular arithmetic operations over integer rings of the form Z2. The proposed techniques have successfully been applied to the equivalence checking problem of industrial benchmarks. The experimental results on different applications have shown significant advantages over existing bit-level and also word-level equivalence checking techniques.